we are looking for RISC-like instruction set architecture Processor implemented by VHDL using Von Neumann Architecture. It has some ALU, Memory, and Control Unit operations. And these operations are specified exactly in the PDF attached below. We also want a schematic design for these 5-Pipelined stages of the processor. The delivery should be before Friday midnight (27/05/2022).
Design a device that will work as scanner/printer machine. If the switch is on, the device will read a sentence of 10 characters from a scanner which is connected serially. The sentence is saved in external RAM memory. When the switch is off, the device will print 20 characters from internal ROM serially. The user of the device should turn the switch on or off. Initially the switch is ON. Write all your assumptions clearly. Use the 8051 for your design and use 1,200 baud rate. 3. Write a code that read characters from a device called line generator connected to the serial port of 8051 and convert the uppercase characters to lowercase. Use baud rate 19,200. 4. Design a device using 8051 to let the user choose between 9,600 or 19,200 baud rates. The user will print serially the information r...
Assalam o alaikum !!! We are looking for electrical engineers to join our team and work on different projects related to following domains of electrical engineering: 1) Control System 2) Satellite communication 3) Radio frequency and microwave circuit design 4) VLSI techniques 5) Radar theory and satellite communication 6) Intelligent and adaptive systems 7) Digital design 8) Asic design Freelancers must be proficient in following: 1) Matlab / Simulink 2) Proteus 3) Multisim 4) pspice 5) LTspice 6) VHDL/Verilog coding What I am expecting: 1. Dedication to the work 2. On time delivery of work without any delay 3. Well arranged and properly formatted reports with plagiarism count below 10%
using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++
I need code for zero crossing detection, synced with pwm generator with fixed duty cycle but variable frequency in esp-idf. I need it urgently Its a signal generator like square wave or pwm with fixed 50% duty cycle, but its frequency needs to be varied from 500 to 100Khz (might be done using ledc_timer_1_bit) but when there is zero crossing, its signal needs to be stopped so that igbt should'nt conduct at zero crossing,