se trata de hacer unas practicas en la placa KCU105 de Xilinx utilizando el modulo AD9361 en simulink para exportar a código HDL para implementar en físico el sistema operativo de Windows
I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail
I need and expert who can Design PSR-aware low dropout regulator using PMOS/NMOS/both focus on PSR improvement, Provide schematic,simulation results,charts and graphs, Provide result analysis
Hello I have a red pitaya board, and want to learn to build linux and modify device try for it. I would also like to clarify some of my doubts about linux build.
It is about doing some practices on the XCIN10 KCU105 board using the AD9361 module in simulink to export to HDL code to physically implement the Windows operating system
Need someone who has the PLDa PCIe ipcore license for Xilinx Vivado to help compile a FPGA project. I'll give you the source code. You compile and give me the bit file and compiled project.
we noted in Section 2.5, the power ampliﬁer designis based on a Melexis application note ([Mel04]), recallFigure 3. We used the output stage of the TI S4100 readermodule in the base board to drive the power ampliﬁer in-put. We did not invest any effort in impedance matchingsince the power ampliﬁer input is voltage driven. Wemanufactured the PCB for the power ampliﬁer using thesame technique as use...
The test program used for transmited data between DDR4 of FPGA and DDR4 of PC adopted windows 10 or win7 system via PCIe 3.0 x8. A tested result shows that the speed of PCIE3.0 *8 is over 7GB/s , which is tested by xilinx Kcu1500 FPGA board. However, the speed under win7 / win10 is only about 4.5-4.9GB/s. The minimum speed threshold should be 5.5 GB/s. And it will be helpful if the speed...