Designing a hash checker in verilog

Hi I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 8 years experience to use ISE, NCverilog, XPS tools and completed many digital design projects. Recently I have completed 10G data traffic project where all the code is written in Verilog/VHDL. Next we are embedding AES into the code. I can do this project. I have also two FPGA boards ML605 and SP605 where I can test model and give you fully working FPGA prototype. Further we can discuss.

Dear! I have three years experience in ASIC field, good command in RTL design and coding with Verilog. I've been working for Dolphin Technology Inc (at San Jose, CA) since I graduated. Currently I'm designing RTL for PCI-Express controller core for my company. I think I'm a suitable candidate for your project. Thank you for your consideration and waiting to hear from you.

Hello, I have a long experience with FPGA based hardware and software design and wish to work with you on this project. Since I did not have a clarity on the details of the project I just quoted in your budget. Can you give some more details, like which HASH, is it an integrated processor for software etc? I will adjust the bid and timing according to that... Thanks Vinod

I have lots of work experience in digital design using Verilog, VHDL & then verification of ASIC & SoC using HVL like System Verilog, VERA,OVM, UVM, VMM, etc. Have experience building verification enviorment from scratch & developing components like driver, monitor, checker, scoreboard, test plan, test cases, coverage closure, etc. I can assure you that if given the opportunity, I will strive to complete it with desired quality & on time. I am looking forward to a long term association with you. Regards, Vasu

i am working for 3 years on digital design and FPGA applications using Verilog and VHDL for wireless and security applications

having 4 years of experience in FPGA based designs and verilog based implementation, verification and testing.

I am working as a RTL design and verification engineer. Having sound knowledge in verilog and systemverilog.