Pin planning for JESD204B converter Design

Project goal is a detailed pin planning and block diagram for a JESD204B data converter application. The following components will be disclosed to applicants: - ADC - FPGA - PLL The interface will work at speeds up to 12.5Gb/s. ADC sample rate will be up to 1Gs/s The deliverables for this project are: - Spreadsheet with pin assignments from FPGA to ADC - Spreadsheet with pin assignments from FPGA to PLL - Spreadsheet with pin assignments from PLL to ADC The pin planning shall be done in such a way that 2 ADCs of the same type can by synchronized in the final design.