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Design Record Portfolio

£250-750 GBP

Cerrado
Publicado hace casi 5 años

£250-750 GBP

Pagado a la entrega
VHDL and FPGA system using vivado program.
ID del proyecto: 19433767

Información sobre el proyecto

7 propuestas
Proyecto remoto
Activo hace 5 años

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7 freelancers están ofertando un promedio de £515 GBP por este trabajo
Avatar del usuario
Dear sir I have more than 10 years experience in digital design using vhdl and Xilinx vivado and i am the top rated vhdl designer, please check my profile also please message me so that we can discuss
£250 GBP en 1 día
4,9 (401 comentarios)
7,8
7,8
Avatar del usuario
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
£555 GBP en 10 días
4,9 (83 comentarios)
6,3
6,3
Avatar del usuario
I've more than four years of experience in FPGA design using VHDL. I've done multiple signal processing projects, communication protocols. I've done similar Design record also which is divided into Milestone 1,2,3. for that I , myself, ran the simulation and captured the waveforms and added into the document along with all other details
£555 GBP en 15 días
5,0 (2 comentarios)
3,3
3,3
Avatar del usuario
hi I have worked on zynq FPGA and have used vivado to implement projects. Kindly consider me for your project and explain in detail about your project. Thanks
£577 GBP en 10 días
5,0 (2 comentarios)
2,9
2,9
Avatar del usuario
Hi guys, I have five years experience FPGA design. I am working on Arrive technologies company. And my company flow working is similar with your requirement. So, I think I can help you. Below is my exp: - DDR. - Pcie. - OTN network - QDMA - Serdes - Synthesis timing closure ... Thanks, Vu
£555 GBP en 7 días
0,0 (0 comentarios)
0,0
0,0
Avatar del usuario
I have been working on VHDL/Verilog for more than 5 years and have relevant experience in Xilinx FPGA and Vivado tools. I have good experience with interfaces like SD, NAND and SATA and worked with Video interfaced projects in tha past
£555 GBP en 30 días
0,0 (0 comentarios)
0,0
0,0
Avatar del usuario
dear, I can implementation of your algorithm if I know about your project. normally , I suggest requirement and then design algorithm and then write VHDL codes, then synthesis and simulation and finally implementation and create bit file based on your hardware. please share your documents with me for best work. thank you
£555 GBP en 10 días
0,0 (0 comentarios)
0,0
0,0

Sobre este cliente

Bandera de UNITED KINGDOM
portsmouth, United Kingdom
0,0
0
Miembro desde may 4, 2019

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