Design and Simulation of Combinatorial and Sequential Digital Systems Using VHDL Behavioral Modeling and the Xilinx Vivado Design Suite

1)Using VHDL and the Xilinx Vivado Tools, design and implement a 4-bit ALU whose functionality is compliant with the TTL MSI 74LS381A specifications. The design must use a VHDL behavioral modeling coding style and can include concurrent and sequential statement types. Source code modules must include liberal commenting to clarify and explain function and operation your code. 2) Create a test bench VHDL module and use the Vivado Simulator to test/verify proper operation of the ALU’s functions with all input data patterns specified in the 74LS381A functional table. Recommendation: to make comparison of simulated results to those listed in the functional table easier, apply the external stimulus input patterns in the same “row” order as inputs are listed in the functional table, and configure the radix of outputs as “binary”. 3) Create an XDC file to map your circuit IOs to the Basys3 board. Use slide switches for the 4-bit input data operands, carry in, and functionality mode selection bits (S2-S0). Use LEDs to display the outputs: result and carry out. 4) Synthesize and implement your design in Vivado, then generate bit stream & program the FPGA board. 5) Test and verify the operation of your design on the FPGA board for all arithmetic & logical operations using a subset of input data patterns you choose from the functional table.