Design sine-wave generator on FPGA

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hi, I've more than four years of experience in FPGA/ASIC Design using VHDL, Verilog/System Verilog. I've developed multiple systems with high speed DDS. I've worked with ADC and DAC including data capture and data generation in low and high speed (upto 1GSPS). I've developed multiple communication protocol such as SPI, I2C. So I can help you for this project very easily.

I have expertise in RTL Design since 4 years and have well versed with FPGA Design. Previously worked on project like same spec.

Hello there i have good expertise with Analog to Digital Conversion and Signal Processing. I also have designed the Sigma Delta ADC and implemented/tested on FPGA device. Let me know your interest!

Hi there, I have checked the details. I have rich experience with FPGA, Verilog / VHDL. Please initiate the chat so we can discuss this job in detail.

Hello, Just a few questions: 1. What chip would be used, or is the RTL design all that is needed? 2. Which IDE should be used? Xilinx, Quartus...? 3. What kinds of verification tests should be used? 4. What is the value of the main clock? 5. What amount of documentation/comments is needed? Best regards, Uros Maric