Modified MIPS pipelined processor in system verilog

You will implement a subset of the pipelined MIPS architecture in system verilog. You will implement a functioning outline of the pipelined processor for a small set of instructions, including: decoding all the instructions you will encounter in this project, implementing most of the MIPS pipeline, correct implementation of arithmetic and logic operations, and implementing a hazard detection and avoidance unit for these instructions. You will implement a five-stage MIPS pipeline, which is the most common organization for MIPS : 1. Fetch 2. Decode 3. Execute 4. Memory 5. Writeback Your design should contain a program counter, a separate data and code memories, a register file, an ALU, and any other components needed, along with the instruction decode and control circuits and a hazard unit. The pipeline should: fetch instructions to execute from the code memory and increment the program counter by 4; decode each instruction; select arguments from the register file; compute results; do nothing in the memory stage; and store results back in the register file. Your processor must correctly execute all of the highlighted instructions in Table 1(attatched). Testing Write a test program in MIPS assembly that fully tests all of the features you have implemented. Our testing programs for this project will include a mixture of instructions from Table 1. This is a critical step, and you will use the MIPS testbench given by the textbook and shown in this section. The MIPS testbench loads a program into the memories. The program in Figure 3 exercises some of the instructions by performing a computation that should produce the correct answer only if all of the instructions are functioning properly. Specifically, the program will write the value 7 to address 84 if it runs correctly, and is unlikely to do so if the hardware is buggy. This is an example of ad hoc testing. The machine code is stored in a hexadecimal file called [login to view URL], which is loaded by the testbench during simulation. The file consists of the machine code for the instructions, one instruction per line. Documentation The design document should include a block diagram showing all the major changes in the given architecture. You need not completely draw wires for control logic signals, but should indicate which components take control inputs, and give names to all control signals. Also include a description of your control and instruction decoding logic. For each control logic signal (or group of related control logic signals) you should provide (a) a brief description of what the signal does, e.g. what the values of the control signalmean (b) a truth table showing what value the signal takes for each possible opcode.