A result oriented, self-starter and proactive individual interested in technology development as a FPGA/ASIC Design Engineer, offering expertise to successfully develop technological solutions to contribute to the success and advancement of your organization.
PROFESSIONAL HIGHLIGHTS
• Registered as EIT, Professional Engineers Ontario (PEO)
• Over 2 years of experience in developing RTL codes using VHDL/Verilog HDL for digital circuitry
• One year experience in Application Support to troubleshoot the issues and provide the fixes
• Hands-on knowledge in Simulation, Synthesis, Static timing closure
• Well-versed in using Xilinx ISE/EDK, Modelsim simulator, VCS,DVE
• Experience in writing and executing test benches to verify complex designs
• Extensive knowledge on UVM Verification Methodology
• Working knowledge on interfaces i.e. Ethernet, I2C
• Provided support for multiple servers in linux
• Self-motivated and able to work effectively both independently and in a team environment
• Extensive Knowledge on FPGA designing to implement high-speed Digital circuit design, including floor planning, part placement and routing, constraint generation, and signal integrity analysis