Hi, I have been working on Quartus and Xilinx for over 4 years in Verilog. Your requirement is a watch dog timer functionality. It is used in most of the router applications to detect if the system is hung. A trigger pulse is sent in a fixed duration and if the pulse don't come then the system has to be reset. I am familiar with this implementation and have done this many a time.
I am almost kind of ready with the code and I have compiled it in Quartus II as well.
If you can award me the project, I can provide you the code immediately and help you in getting doubts cleared as well. Hoping to hear from you.