Find Jobs
Hire Freelancers

Need a Verilog Coder for simple project.

$10-30 USD

Cerrado
Publicado hace casi 6 años

$10-30 USD

Pagado a la entrega
I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.
ID del proyecto: 17318672

Información sobre el proyecto

20 propuestas
Proyecto remoto
Activo hace 6 años

¿Buscas ganar dinero?

Beneficios de presentar ofertas en Freelancer

Fija tu plazo y presupuesto
Cobra por tu trabajo
Describe tu propuesta
Es gratis registrarse y presentar ofertas en los trabajos
20 freelancers están ofertando un promedio de $23 USD por este trabajo
Avatar del usuario
Dear sir I have more than 10 years experience in embedded systems design using Verilog please check my profile also please message me so that we can discuss best regards
$30 USD en 1 día
4,9 (468 comentarios)
8,0
8,0
Avatar del usuario
Hello! Please check my profile and my reviews to know a bit about me and my work. It would be great if I could help you out. Thank you!
$25 USD en 1 día
4,9 (98 comentarios)
6,3
6,3
Avatar del usuario
Expertise in verilog with a substantial background in FPGAs. I have completed various projects related to this field and can provide you your complete task in decided time frame with quality work. We can discuss further details in the message box Regards
$25 USD en 2 días
4,9 (77 comentarios)
5,3
5,3
Avatar del usuario
Hi, I am a professional electrical engineer. I am an expert in designing and simulating digital systems and writing Verilog and VHDL codes I also have both modelsim and Quartus to test and confirm working code. You can see some of my work in my portfolio about the subject and the opinion of people I worked with in my reviews Thanks
$25 USD en 1 día
4,7 (28 comentarios)
5,3
5,3
Avatar del usuario
Hi, I have been working on Quartus and Xilinx for over 4 years in Verilog. Your requirement is a watch dog timer functionality. It is used in most of the router applications to detect if the system is hung. A trigger pulse is sent in a fixed duration and if the pulse don't come then the system has to be reset. I am familiar with this implementation and have done this many a time. I am almost kind of ready with the code and I have compiled it in Quartus II as well. If you can award me the project, I can provide you the code immediately and help you in getting doubts cleared as well. Hoping to hear from you.
$20 USD en 1 día
5,0 (3 comentarios)
0,2
0,2
Avatar del usuario
Presently doing project on FPGA using verilog.. Hope I can help you
$15 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
Avatar del usuario
Versatile knowledge in both vhdl & verilog. Having 10+ years of industrial experience Relevant Skills and Experience Versatile knowledge in both vhdl & verilog. Having 10+ years of industrial experience
$45 USD en 1 día
0,0 (0 comentarios)
0,0
0,0

Sobre este cliente

Bandera de UNITED STATES
United States
0,0
0
Miembro desde jul 8, 2018

Verificación del cliente

¡Gracias! Te hemos enviado un enlace para reclamar tu crédito gratuito.
Algo salió mal al enviar tu correo electrónico. Por favor, intenta de nuevo.
Usuarios registrados Total de empleos publicados
Freelancer ® is a registered Trademark of Freelancer Technology Pty Limited (ACN 142 189 759)
Copyright © 2024 Freelancer Technology Pty Limited (ACN 142 189 759)
Cargando visualización previa
Permiso concedido para Geolocalización.
Tu sesión de acceso ha expirado y has sido desconectado. Por favor, inica sesión nuevamente.