Design and implementation of pipeline processor

I have done 16bit RISC processor project using Xilinx verilog without pipelining, but I can also do the same with pipelining within four days.

Yes sir i can surely do Design and implementation of pipeline processor for you sir let me know i have done last month .

Implementation of RISC processor using FPGA: RISC Processor will be implemented in FPGA using VHDL/Verilog HDL. The design will be synthesized using Vivado IDE 2017.4 tool and the effective resource utilization will be submitted as per Xilinx estimation. The design functionality will be verified using Vivado ISIM simulator and the results will be submitted. The user document will be provided to test the design, and technical document will be given which will explain the design implementation.

I'll be using my own experience and proven plan in related projects( attached in my portfolio), to accomplish the task in an optimized way with regard to budget, time and results' quality. ------------------------------------------------------------------------- (Deliverables): Deliverable #1: Verilog source codes for all modules/blocks Deliverable #2: RTL Gate-level schematic design. Deliverable #3: Post place and route simulation and testing. Deliverable #4: Power Analysis. Deliverable #5: Timing (Speed) Analysis. Deliverable #6: Real-time FPGA Implementation -------------------------------------------------------------------------------------------------- (Why choose me? ) I have mastered the best routine to hardware-describe pipelined-processors to result in optimized (Data & Instruction memory, register files, , arithmetic cores and data paths) in addition to high throughput(speed) and lowest power consumption. I have implemented extremely-related projects (attached in my portfolio), as follows; (1)- 32-bit pipelined MIPS processor in Verilog , implemented using Spartan 3E FPGA and Nexys2 Board. (2)-16 bit single cycle processor in Verilog, implemented using Cyclone IV latera FPGA. ---------------------------------------------------------------------------------- (My question for you): Do you have a specific preference for the FPGA used for implementation? Also, may you provide me with the instruction set? It will help estimate the total budget/timeframe