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Build an ALU with testbench

$10-30 USD

Terminado
Publicado hace más de 7 años

$10-30 USD

Pagado a la entrega
Build an ALU with testbench. Compile in Quartus to get size and timing information. Simulate in ModelSim
ID del proyecto: 11728359

Información sobre el proyecto

15 propuestas
Proyecto remoto
Activo hace 8 años

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A proposal has not yet been provided
$45 USD en 1 día
5,0 (294 comentarios)
7,6
7,6
15 freelancers están ofertando un promedio de $30 USD por este trabajo
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please visit my profile to see my expertise over this area. Thanks
$10 USD en 0 día
4,8 (90 comentarios)
6,3
6,3
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Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency
$50 USD en 1 día
4,9 (5 comentarios)
4,6
4,6
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i am having good knowlede about Verilog and VHDL programming and have done number of projects using Verilog .I used quartus for programming and used model sim fo simulating our model.i have done number of project usinf CPLD and FPGA.i will do your work easily and accurately as soon as possible.
$13 USD en 1 día
4,8 (2 comentarios)
2,5
2,5
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Hello sir, I am a hardware engineer. I've done many projects on IP core using Verilog. Please see reviews on my profile. It would be my pleasure to work on your project. Please contact me to discuss the details. Thank you for your consideration
$10 USD en 0 día
5,0 (3 comentarios)
2,5
2,5
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I can implement your request within 24 hours, I guarantee you satisfaction with the work. I'm a student at the Faculty of Engineering and the field of my studies
$50 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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i'm an electronics engineer with experience in digital design , i've implemented a full microprocessor with mips instruction set in VHDL , but i don't have quarts i can only simulate it in modelsim
$35 USD en 2 días
0,0 (0 comentarios)
0,0
0,0
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I have already done a processor with test bench so it is very easy for me....................................................................................................................................
$25 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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A proposal has not yet been provided
$35 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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Hi guys, I have just completed one project similar with your project. Can you contacted me to get my information for further discussion. Thanks, Vu
$25 USD en 1 día
0,0 (0 comentarios)
0,0
0,0

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Bandera de UNITED STATES
dayton, United States
5,0
1
Miembro desde oct 7, 2016

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