Hi,
I would like to take up this opportunity, below are the highlights of my experiences,
--> Hands-on experience in ASIC/FPGA RTL Coding using Verilog/VHDL
--> Hands-on experience in Xilinx/Altera FPGA devices
--> Vivado/Quartus II tool flows, including debug tool like ILA
--> Good understanding in Timing analysis, Clock Domain Crossing, Timing Constraints
--> Good debugging and hardware experience
Please consider my proposal, and get back to discuss more and get start!
Thanks
Prasanth S