Verilog Simulation and Testbench Modification Project
I am looking for a freelancer who can assist me with a Verilog simulation project. Specifically, I need someone who can modify an existing Verilog code to create a basic level testbench.
I have two codes: Clock divider, 7segemnt, and I need to apply them
Required Skills and Experience:
- Strong proficiency in Verilog programming language
- Experience with Verilog simulation and testbench design
- Familiarity with ModelSim tool or equivalent
- Ability to communicate effectively and work collaboratively
If you have the necessary skills and experience, please apply for this project.
Hello,
I am VLSI Verification Engineer by Profession with 3 year of experience in Design and Test bench development with VHDL, Verilog, systemVerilog and UVM.
Also I can help you how to use MODELSIM for design and Verification.
I can easily help you to implement/resolve your code for clock divider and 7 segment.
We can acheive 100% code coverage with testbench if you needed.
Kindly message me to discuss further.
Regards
Ashish
$40 USD en 3 días
5,0 (1 comentario)
0,6
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3 freelancers están ofertando un promedio de $52 USD por este trabajo
Hello,
I have experience in FPGA coding using Verilog HDL, I have experience with multiple FPGAs and tools such as Xilinx and Quartus, I know I can help you with your project, I can finish it within a day.
Feel free to contact me for further details, I look forward to working with you.
Have a great day